1. Field of the Invention
The present invention relates to an operation analysis method of a semiconductor integrated circuit, particularly a large scale and high speed drive LSI (Large Scale Integration).
2. Related Background Art
While multiple-function and low power consumption appliances have dominated the market in recent years, their components, LSIs, are also required to consume less power. As one of the lower power consumption design techniques used for such LSIs, substrate bias control technology is proposed (Patent document 1).
FIG. 18 shows an example of the substrate bias control technology in the CMOS design using a silicon substrate. A deep N well 210 is formed on a P-type silicon substrate 201, and further inside thereof, an N well 202 and a P well 203 are formed. In the N well 202, a P-channel transistor 204 and an N well substrate contact 206 are formed. In the P well 203, an N-channel transistor 205 and a P well substrate contact 207 are formed. The substrate contacts 206 and 207 are respectively connected to dedicated control wirings VBP and VBN. That is, such a configuration is provided that controls substrate potential with independent wiring from power supply wiring VDD and ground wiring VSS respectively connected to transistor sources 208 and 209.
For example, a case of performing substrate bias control regarding the P-channel transistor 204 will be described. When a potential lower than the power supply wiring VDD is provided to the control wiring VBP, electric charge in the channel is depleted, so that although a transistor operating speed becomes slow, power consumption due to leak current and the like decreases. Conversely, when a potential higher than the power supply wiring VDD is provided to the control wiring VBP, power consumption increases but the transistor operating speed becomes fast. Likewise, when a potential higher than the power supply wiring VSS is provided to the control wiring VBN, electric charge in the channel is depleted, so that the transistor operating speed becomes slow while reducing power consumption due to leak current and the like. Conversely, when a potential lower than the power supply wiring VSS is provided to the control wiring VBN, power consumption increases but the transistor operating speed becomes fast.
Thus, the substrate bias control technique is characterized in that by controlling the substrate potential at the N well and P well by control wiring which is independent of the power supply wiring VDD and the ground wiring VSS, priority of transistor operating speed and power consumption during operation of the LSI is controlled, and power consumption can be reduced depending on the speed required.
On the other hand, because of the demand for multiple functionality, a number of circuit elements are mounted on one LSI by LSI microfabrication technology. As a result, the total amount of current consumed by the circuit elements increases, while on the other hand an operating frequency of the circuit elements is rising, thereby posing conspicuous problems of power supply noise and substrate noise of the LSI. In view of this, there are proposed methods of predicting the power supply noise and the substrate noise from LSI design information (see Patent Document 2 and Patent Document 3).
As the way the power supply noise and the substrate noise affect LSI, there is the conspicuous problem of affecting delay time of a digital circuit element, in addition to effects on conversion accuracy of an analog/digital converter, PLL jitter, and the like. Consequently, there is proposed a method of predicting the delay time based on the waveform of the power supply noise (see Patent Document 2).
FIG. 19 shows a conventional example of the method. A dynamic potential analysis S301 is performed by using circuit information 308 such as a net list, layout information, parasitic resistance, and parasitic capacity. Based on a resultant potential waveform 309 thus obtained, through an abstracting step S302 which abstracts the potential, a delay calculation S305 is performed by using calculated potential abstracting information 310, thereby calculating delay information 311.
(Patent Document 1) Japanese Unexamined Patent Publication No. 11-126827
(Patent Document 2) Japanese Unexamined Patent Publication No. 2005-4268
(Patent Document 3) Japanese Unexamined Patent Publication No. 2005-4245
In the foregoing delay calculation technique that take the potential waveform into consideration, as shown in FIG. 20, it is assumed that the power supply VDD and the N well substrate contact 206 are connected and that the ground VSS and the P well substrate contact 207 are connected. In this case, since the potentials of the power supply and ground are the same as the substrate potential, it was possible to predict malfunction of a circuit such in delay time by using the power supply potential and the ground potential.
However, as mentioned above, in the semiconductor integrated circuit using the substrate bias control technology, because the power supply potential and the ground potential are different from the substrate potential, the substrate potential fluctuates differently depending on the operating status of the circuit elements. Therefore, it is not possible to predict the circuit malfunction from the power supply potential and the ground potential alone. That is, differently from the conventional design where the power supply is connected to the substrate, the power supply noise and the substrate noise become independent of each other in the substrate bias control design, so that it is also necessary to take into consideration effects on circuit delay due to the substrate noise.